SoC 설계

SystemVerilog

yztech 2024. 4. 21. 03:30
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Introduction

개요

Data types

Variables

Converting logic to real, or real to logic

Arrays

배열(Array)
배열 시스템 함수들 (Array system functions)

RTL coding

Procedural blocks

변환 (Casting)

태스크, 함수

Interface

modport

Simulation

Testbench

Verilog

Icarus Verilog, GTKWave
timescale, delay

Misc

Modelsim

Modelsim Warning (vsim-PLI-3691)

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