SoC 설계
SystemVerilog
yztech
2024. 4. 21. 03:30
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Introduction
Data types
Variables
Converting logic to real, or real to logic
Arrays
배열(Array)
배열 시스템 함수들 (Array system functions)
RTL coding
Interface
Simulation
Verilog
Icarus Verilog, GTKWave
timescale, delay
Misc
Modelsim
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